THE OPTIMIZATION OF ENERGY-EFFICIENCY AND RELIABILITY USING COMPLEX REDUNDANCY IN COMPUTING SYSTEMS
Науковий журнал «Радіоелектроніка, інформатика, управління»
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THE OPTIMIZATION OF ENERGY-EFFICIENCY AND RELIABILITY USING COMPLEX REDUNDANCY IN COMPUTING SYSTEMS |
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Kamenskih, A. N.; Perm National Research Polytechnic University, Russia. Tyurin, S. F.; Perm National Research Polytechnic University, Russia. |
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energy-efficiency; reliability; fault-tolerant; self-timed circuits; redundancy at transistor-level; complex redundancy. |
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Context. The increase of energy-efficiency and reliability of computing systems is still important task in 21st century. It is especially<br />important in the field of computing systems for aerospace because both the radiation-tolerance should be provided and the<br />energy-consumption are very limited. Moreover, the developers should take care about performance of a computing system. Therefore, all of this result in difficult optimization task with key-parameters – reliability, energy-efficiency and performance in conditions<br />of existing technologies limits.<br />Objective. The solution of optimization task – the synthesis of digital devices that can work in wide temperature and voltage<br />range at restrictions on reliability probability and performance.<br />Method. Delay-insensitive (or Self-timed according to Russian terms) circuits can stable operate in delay variation including operation<br />under ultra-low-supply-voltage (ULSV). That is why it became a good solution for considered task. To increase reliability in<br />the critical fields of application, the redundancy is often used. For example, the triple modular redundancy or the Hamming codes.<br />However, the implementing of these methods in delay-insensitive circuits faces problems – excessive increase of complexity or delays<br />in critical paths. In addition, the Muller’s model are not provide possibilities to take into account failures as normal part of system<br />operations. Thus, the definitions of fault-tolerance and semi-modularity (the basic feature of delay-insensitive circuits) have a<br />conflict. In the paper the method of redundancy at transistor level was developed. The combination of proposed and known methods<br />allows receiving new efficient solutions.<br />Results. The model of fault-tolerant self-timed circuits was developed. The method of complex redundancy for self-timed circuits<br />was proposed. This method provides synthesis of digital devices with optimization in key parameters.<br />Conclusions. The research proved that only the combination of methods provide the achievement of function’s optimum. It is interesting<br />task to expand the object of research to synchronous and globally asynchronous locally synchronous computing systems in<br />further research. |
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Zaporizhzhya National Technical University 2018-12-07 16:07:43 |
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application/pdf http://ric.zntu.edu.ua/article/view/149805 |
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Radio Electronics, Computer Science, Control; No 3 (2018): Radio Electronics, Computer Science, Control |
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ru |
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Copyright (c) 2018 A. N. Kamenskih, S. F. Tyurin |
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