Low-power architecture for CIL-code hardware processor
Vernadsky National Library of Ukraine
Переглянути архів Інформація| Поле | Співвідношення | |
| Title |
Low-power architecture for CIL-code hardware processor
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| Creator |
Chapyzhenka, A.
Ragozin, D. Umnov, A. |
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| Subject |
Інструментальні засоби і середовища програмування
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| Description |
In the article the authors present the architecture of a hardware CIL processor, which is capable to execute CIL instructions as native code. The CIL hardware engine is implemented on the top of the low-power DSP architecture, and the CIL processor has two execution cores: DSP and CIL. Such solution allows to execute both CIL and DSP instruction sets as native instructions sets and gain performance in common multimedia tasks. Therefore, the DSP-based CIL processor may be targeted for multimedia digital home and even embedded applications. The research was sponsored by RFP 2 Microsoft Corp. grant.
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| Date |
2008-07-28T18:54:51Z
2008-07-28T18:54:51Z 2005 |
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| Type |
Article
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| Identifier |
Low-power architecture for CIL-code hardware processor/ A. V. Chapyzhenka, D.V. Ragozin, A.L. Umnov // Проблеми програмування. — 2005. — N 4. — С. 20-38. — Бібліогр.: 16 назв. — англ.
1727-4907 http://dspace.nbuv.gov.ua/handle/123456789/1372 004.273 |
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| Language |
en
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| Publisher |
Інститут програмних систем НАН України
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