Enhancing Path Delay Fault Coverage by Weighted Pseudorandom Test Generation
Електронного архіву Харківського національного університету радіоелектроніки (Open Access Repository of KHNURE)
Переглянути архів Інформація| Поле | Співвідношення | |
| Creator |
Gjermundnes, O.
Aas, E. J. |
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| Date |
2014-10-29T10:08:29Z
2014-10-29T10:08:29Z 2008 |
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| Identifier |
Gjermundnes, O. Enhancing Path Delay Fault Coverage by Weighted Pseudorandom Test Generation/ O. Gjermundnes, E. J. Aas // Радиоэлектроника и информатика : науч.-техн. журн. – Х. : Изд-во ХНУРЭ, 2008. – Вып. 1. – С. 13–18.
http://hdl.handle.net/123456789/1405 |
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| Description |
The implementation of a system for analyzing circuits with respect to their path-delay fault testability is presented. It includes a path-delay fault simulator, and an ATPG for path-delay faults combined into a test tool. The test tool is used to evaluate the performance of several different test vector generators. The test generators exploit weighted pseudo-random stimuli generation, based on arithmetic BIST and SIC patterns. The main goal is to find efficient heuristics that improves path-delay fault detection efficiency in terms of test time. We show that weighted ABIST stimuli are productive for detecting the K-longest path-delay faults for most circuits. On the average, we obtained fault coverage of 92.6% for the 20.000 longest paths on iscas’85 circuits. Index Terms − Built-in testing, Fault diagnosis, Automatic testing. |
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| Language |
en
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| Publisher |
ХНУРЭ
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| Subject |
Built-in testing
Fault diagnosis Automatic testing |
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| Title |
Enhancing Path Delay Fault Coverage by Weighted Pseudorandom Test Generation
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| Type |
Article
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