Models and Methods for Verification and Diagnosis of SoC HDL-code
Електронного архіву Харківського національного університету радіоелектроніки (Open Access Repository of KHNURE)
Переглянути архів Інформація| Поле | Співвідношення | |
| Creator |
Hahanov, V.
Gharibi, W. Litvinova, E. Chumachenko, S. |
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| Date |
2014-11-14T09:03:21Z
2014-11-14T09:03:21Z 2010 |
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| Identifier |
Models and Methods for Verification and Diagnosis of SoC HDL-code / V. Hahanov and all // Радиоэлектроника и информатика : науч.-техн. журн. – Х. : Изд-во ХНУРЭ, 2010. – Вып. 4. – С. 36-46.
http://hdl.handle.net/123456789/1554 |
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| Description |
Xor-metrix for object relations in a vector logic space and a structural testing model are proposed. Assertion-based models and methods for the verification and diagnosis of HDL-code functional failures, which make possible to reduce considerably time-tomarket of software and hardware, are developed. An architectural model of multimatrix reduced logical instruction set processor for embedded diagnosing is offered. |
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| Language |
en
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| Publisher |
ХНУРЭ,
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| Subject |
HDL-code
verification Xor-metrix time-to-market |
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| Title |
Models and Methods for Verification and Diagnosis of SoC HDL-code
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| Type |
Article
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