A Method of High-Level Synthesis and Verification with SystemC Language
Електронного архіву Харківського національного університету радіоелектроніки (Open Access Repository of KHNURE)
Переглянути архів Інформація| Поле | Співвідношення | |
| Creator |
Obrizan, V.
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| Date |
2014-11-14T09:09:43Z
2014-11-14T09:09:43Z 2010 |
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| Identifier |
Obrizan, V. A Method of High-Level Synthesis and Verification with SystemC Language / V. Obrizan // Радиоэлектроника и информатика : науч.-техн. журн. – Х. : Изд-во ХНУРЭ, 2010. – Вып. 4. – С. 47-50.
http://hdl.handle.net/123456789/1555 |
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| Description |
This paper presents a method for automatic RTL-interface synthesis for a given C++ function as well as for a given SystemC-interface. This task is very im-portant in High-Level Synthesis design flow where design entry is usually done in some abstract language (e.g. C++). As a source high-level description targets different SoC architectures or protocols, so it is needed to generate relevant pin-level interfaces and protocols automatically. |
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| Language |
en
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| Publisher |
ХНУРЭ
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| Subject |
computer languages
high level synthesis system-level design system testing |
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| Title |
A Method of High-Level Synthesis and Verification with SystemC Language
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| Type |
Article
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