Verification Challenges of Clock Domain Crossings
Електронного архіву Харківського національного університету радіоелектроніки (Open Access Repository of KHNURE)
Переглянути архів Інформація| Поле | Співвідношення | |
| Creator |
S. Zaychenko, D. Melnik, O. Lukashenko
|
|
| Date |
2016-07-06T09:15:14Z
2016-07-06T09:15:14Z 2008 |
|
| Identifier |
S. Zaychenko Verification Challenges of Clock Domain Crossings/D. Melnik, S. Zaychenko, O. Lukashenko//Proceedings of IEEE East-West Design & Test Symposium (EWDTS’08)
http://hdl.handle.net/123456789/3137 |
|
| Description |
Only the most elementary logic circuits use a single clock. Today’s system-on-chips (SoC) have dozens of asynchronous clocks. There are a lot of software programs to assist in creating of multimillion-gate ASIC/FPGA circuits, but designer still has to know reliable design techniques to reduce the risk of CDCrelated design re-spins. Moreover, the most relevant literature does not cover CDC-related issues and approaches to prevent appropriate costly silicon bugs. This paper discusses typical verification problems occurring within SoC design cycle when multiple clock domains are involved. Critical cases leading to unpredictable SoC behavior during data transfer across clock domains are identified and described. A principle for metastability modeling is suggested. IEEE Computer Society Test Technology Technical Council |
|
| Language |
en
|
|
| Publisher |
EWDTS
|
|
| Subject |
Verification
Clock Domain Crossings |
|
| Title |
Verification Challenges of Clock Domain Crossings
|
|
| Type |
Article
|
|