Dynamic Register Transfer Level Queues Model for High-Performance Evaluation of the Linear Temporal Constraints
Електронного архіву Харківського національного університету радіоелектроніки (Open Access Repository of KHNURE)
Переглянути архів Інформація| Поле | Співвідношення | |
| Creator |
Sergiy Zaychenko, Vladimir Hahanov, Oleg Zaharchenko
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| Date |
2016-07-06T11:22:11Z
2016-07-06T11:22:11Z 2006 |
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| Identifier |
Sergiy Zaychenko Dynamic Register Transfer Level Queues Model for High-Performance Evaluation of the Linear Temporal Constraints/Vladimir Hahanov, Oleg Zaharchenko, Sergiy Zaychenko//Proceedings of IEEE East-West Design & Test Workshop (EWDTW’06)
966-659-113-8 http://hdl.handle.net/123456789/3143 |
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| Description |
Obviously, the verification process is a very complex and a very expensive part of the modern SoC design cycle. This process consists of searching the model for mistakes, causing the design to violate the functional specification, localizing the problems reasons and applying the fixtures. According to the EDA industry experts opinion, the cost of verification in ASIC [1] designs often overheads the 70% of the entire project budget [2]. Such high cost of the system quality is driven by several factors, in particular: – A large amount of missed details and mistakes in the work of SoC designers in the RTL code, verification engineers mistakes in the testbenches, also, the inevitable ambiguities of the original design specification; – drawbacks in the choosen design flows, complicating the bugs localization and fixtures, missing the possibilities for early discovery of the typical problems; – relatively low performance and bugs within the selected automation tools, which reach the quality and performance goals much slower than the input design complexity raises. Resolving these problems altogether and degrading the SoC verification cycle cost is currently a primary goal for the entire EDA world [3]. Leading EDA companies and industry experts are focused on developing the new generation of complex design verification methods, which will be able to: – minimize the human participation in the routine design and verification procedures, which will obviously decrease the probability of mistakes in several times; – lead to catching the largest amount of problems on the early design phases, reducing the average fixture cost; – upgrade the performance and stability of the design verification systems by raising the abstraction level both for the SoC models and for the testing stimulus. There are two basic directions in modern SoC verification methods – dynamic methods [2,4], based on the simulation, and static, or formal methods [5,6], based on the mathematical proof of certain system properties without testing stimulus. There are also hybrid methods [7] used, which assume usage of the simulation and functional coverage results to improve the performance of formal methods. This work is focused on the assertions-based verification technology [8,9], playing its role both in dynamic and formal methods. Today the Assertions Based Verification (ABV) is by all means the most effective verification technology for SoC designs. Assertions provide basic blocks for building functional verification concept. Assertions simply catch a lot of design errors on early phases. This paper suggests new effective algorithmic model for assertions checking within the testbench-based simulation. The algorithms for handling key temporal operators from Property Specification Language (PSL) are described. Paper demonstrates the advantages of the suggested model over existing equivalents - in simulation performance, verification efficiency and model extensibility. |
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| Language |
en
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| Publisher |
EWDTW
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| Subject |
functional verification
assertions linear temporal logic system-on-chip PSL simulation |
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| Title |
Dynamic Register Transfer Level Queues Model for High-Performance Evaluation of the Linear Temporal Constraints
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| Type |
Article
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