Models for Embedded Repairing Logic Blocks
Електронного архіву Харківського національного університету радіоелектроніки (Open Access Repository of KHNURE)
Переглянути архів Інформація| Поле | Співвідношення | |
| Creator |
Hahanov V.I.
Frolov A. Litvinova E.I Tiecoura Yves |
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| Date |
2016-07-06T11:43:19Z
2016-07-06T11:43:19Z 2012 |
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| Identifier |
Hahanov V.I. Models for Embedded Repairing Logic Blocks /Hahanov V.I., Litvinova E.I., Frolov A., Tiecoura Yves //Proceedings of IEEE East-West Design & Test Symposium (EWDTS’2012)
http://hdl.handle.net/123456789/3146 |
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| Description |
If executing with failures within a single chip, the strategy of increasing the reliability of the system based on reconfiguring the functionality can be used, but it has two disadvantages: 1) considerable time of this operation is incompatible with the functioning of critical systems; 2) significant complication of reconfiguring related to the existence of faulty areas on the chips. The second way of improving the reliability of digital systems-on-chips can be the addition of redundant elements to the basic functionality, which are designed to compensate for negative effects of faulty components by their readdressing in the testing loop and fault detection. It requires smaller time cycle in comparison with reconfiguration of functional areas of the chip. Implementation of the second way, proposed in [9-12], lies in adding (modifying) three components (spare functional elements and ports for reading/writing data, advanced multiplexers for switching the first two ones) in SoC functionality, which enables the replacement of faulty elements in the cycle BIST/BISR. The reliability of a discrete area on the chip that implements the complete functionality of a digital system is characterized by the criterion with an exponential distribution depending on the intensity λ of uncorrelated failures, which are constant over time: . e(t)R t A −λ= To consider the reliability of the original structure as a whole, the following estimation can be used [9]: . AM,A(t)R(t)R FU O OA AO × == At that the system is unable to compensate for the failures, resulting it in inoperable state. When considering the complexity of the hardware (Area) of the system with redundancy OA , containing M main components and N spares, to repair functional modules with faults the following conversions of expressions for determining the reliability evaluation BISR R can be used: The models of combinational circuits, focused on solving practical problems of embedded repairing components of the logic units are proposed. The logical circuit is complemented by operational and control automata for modeling digital devices, which increases processing time and hardware costs for creating a wrap of addressable elements. The structures can also be used for hardware modeling functionalities of digital projects by using PLD, which allows improving the performance of software model verification. The proposed solution of embedded gate repair for combinational circuits makes it possible to comprehensively solve the problem of autonomous repairing digital systems on chips due to the time and hardware project redundancy |
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| Language |
en
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| Publisher |
EWDTS
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| Subject |
Models for Embedded
Repairing Logic Blocks |
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| Title |
Models for Embedded Repairing Logic Blocks
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| Type |
Article
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