Error detection and debugging on information in communication system using single electron circuit based binary decision diagram
Vernadsky National Library of Ukraine
Переглянути архів Інформація| Поле | Співвідношення | |
| Title |
Error detection and debugging on information in communication system using single electron circuit based binary decision diagram
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| Creator |
Biswas, A.K.
Sarkar, S.K. |
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| Description |
In digital information error happens in a communication system due to path delay or processing error/delay and can be detected by logical circuit which has been implemented here by binary decision diagrams with single electron movement from root node to leaf node. Binary decision diagrams are the representations of logic functions factored recursively with respect to input variables. Errors in the received information can be detected by the error detection circuit consisting of binary decision diagram circuits. In this technique a maximum errors of four bits can be detected in a received information of 32 bit length. However, by rearranging the received bit patterns it is possible to detect the error(s) in any bit of the received information. Every message signal is transmitted with a tag value. After detecting the error and removing the tag bit(s), the receiver finds out the corrected information.
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| Date |
2017-05-28T14:30:04Z
2017-05-28T14:30:04Z 2003 |
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| Type |
Article
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| Identifier |
Error detection and debugging on information in communication system using single electron circuit based binary decision diagram / A.K. Biswas, S.K. Sarkar // Semiconductor Physics Quantum Electronics & Optoelectronics. — 2003. — Т. 6, № 3. — С. 357-364. — Бібліогр.: 13 назв. — англ.
1560-8034 http://dspace.nbuv.gov.ua/handle/123456789/118049 |
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| Language |
en
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| Relation |
Semiconductor Physics Quantum Electronics & Optoelectronics
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| Publisher |
Інститут фізики напівпровідників імені В.Є. Лашкарьова НАН України
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