Parallel fault simulation on multi-core processors
Електронний архів E-archive DonNTU – (Electronic archive Donetsk National Technical University)
Переглянути архів Інформація| Поле | Співвідношення | |
| Title |
Parallel fault simulation on multi-core processors
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| Creator |
Иванов, Дмитрий Евгениевич
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| Subject |
digital circuit
sequential circuit fault simulation parallel simulation multi-core processo execution thread |
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| Description |
In this paper we propose a fault simulation algorithm that utilizes all cores in multi-core processors. We adapt for multi-core workstation our early proposed distributed fault simulation algorithm. Proposed algorithm uses multi thread execution. The algorithm is based on the well-known «master-slave» approach in which one thread is nominated as a master and controls the calculation on all the other cores of processor. To maximize utilization of the cores a scheme with static fault list partitioning is used. The speed-up coefficient of the simulation time obtained during machine experiments is up to 3.44 times on the quad core system.
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| Date |
2011-10-12T06:44:28Z
2011-10-12T06:44:28Z 2009 |
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| Type |
Article
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| Identifier |
D.E. Ivanov Parallel fault simulation on multi-core processors // «Радіоелектронні і комп’ютерні системи», 2009.- №6(40).- С.109-112. (Четвёртая международная научно-техническая конференция «Гарантоспособные» (надёжные и безопасные) системы, сервисы и технологии, Украина, Кировоград, 22-25 апреля, 2009)
http://ea.donntu.edu.ua/handle/123456789/1443 |
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«Радіоелектронні і комп’ютерні системи»
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