Distributed Fault Simulation and Genetic Test Generation of Digital Circuits
Електронний архів E-archive DonNTU – (Electronic archive Donetsk National Technical University)
Переглянути архів Інформація| Поле | Співвідношення | |
| Title |
Distributed Fault Simulation and Genetic Test Generation of Digital Circuits
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| Creator |
Ivanov, Dmitry
Skobtsov, Yurij El-Khatib |
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| Subject |
digital circuit
genetic algorithm fault simulation parallel simulation multi-core processo islands model |
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| Description |
Fault simulation is on of the most highly compute-intensive task in the technical diagnostics. One of the ways to speed-up this process is a parallelization on the calculation cluster. In this paper a distributed algorithm for fault simulation of digital circuits is presented. It is based on the well-known «master-slave» approach in which one processor is nominating as a master and rules all calculation on the all slave’s processors. To reach the maximal utilization of the processors in the cluster it is used schema with static fault list partitioning.
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| Date |
2011-10-12T07:08:26Z
2011-10-12T07:08:26Z 2006 |
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| Type |
Article
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| Identifier |
Skobtsov Y.A., El-Khatib, Ivanov D.E. Distributed Fault Simulation and Genetic Test Generation of Digital Circuits // Proceedings of IEEE East-West Design&Test Workshop (EWDT’06).- 2006: Sochi.- p.89-94.
http://ea.donntu.edu.ua/handle/123456789/1450 |
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| Language |
en
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| Publisher |
Proceedings of IEEE East-West Design&Test Workshop (EWDT’06).
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