Reduction in the number of LUTs in logic circuit of Mealy FSM
Електронний архів E-archive DonNTU – (Electronic archive Donetsk National Technical University)
Переглянути архів Інформація| Поле | Співвідношення | |
| Title |
Reduction in the number of LUTs in logic circuit of Mealy FSM
|
|
| Creator |
Barkalov, A.A.
Malcheva, R.V. Barkalov, A.A. |
|
| Subject |
finite-state-machine
PR-automaton FPGA LUT EMB synthesis |
|
| Description |
A method is proposed for reducing the hardware amount in logic circuit of Mealy FSM. The methods targets the technology of FPGA. The method is based on using the model of PR-automaton and implementing the system of microoperations with embedded memory blocks. This approach allows reducing the number of LUTs in the FSM’s circuit. The conditions are shown for using the proposed method. |
|
| Date |
2013-04-16T14:00:59Z
2013-04-16T14:00:59Z 2013-04-16 |
|
| Type |
Article
|
|
| Identifier |
http://ea.donntu.edu.ua/handle/123456789/18730
|
|
| Language |
en
|
|
| Relation |
Практика и перспективы развития партнерства в сфере высшей школы;2
|
|
| Publisher |
Донецкий национальный технический университет
|
|