Сontex. The programmable logic integrated circuits FPGA (field-programmable gate array) used realization of the generator of<br />functions LUT (Look Up Table), which is configured by loading a configuration memory for calculating a logic function in perfect<br />disjunctive normal form (PDNF). The LUT dimension determines the technological limitations of Mead and Conway on the number of<br />series-connected MOS transistors. The standard number of LUT inputs for many years was 3 or 4, and 4-LUT is constructed from two 3-<br />LUTs with an additional 1-LUT. However, in many projects, it is required to calculate functions of a large number of arguments. This<br />requires a multi-input LUT, which is built as a decomposition of 3-LUT, 4-LUT. The speed of computing logic functions determines by the<br />delay in the coupling matrices, so this decomposition leads to a decrease in performance. In recent years, the direction of adaptive logical<br />modules (ALM) has been actively developing, in which the user has access to various versions of logical elements for five, six and even<br />seven, eight variables, which leads to an increase in performance. However, the manufacturer’s documentation does not provide a detailed<br />description of the features of such multi-input LUTs, taking into account the Meade-Conway constraints. In addition, there are no estimates<br />of complexity and speed of multi-input LUTs. The analysis of sources allows suggests a further increase in the LUT bit capacity and the<br />convergence of FPGA and CPLD (complex programmable logic devices) capabilities in terms of bit depth. Therefore, studies of the features<br />of constructing multi-input LUTs are relevant and the authors attempted to analyze the implementation of such prospective multi-bit logic<br />Objective. The purpose of this work is to estimate the complexity and speed of the decomposition of a multi-bit LUT.<br />Method. Obtaining expressions for estimating the complexity and speed of decomposition of a multi-bit LUT on a LUT of a lower bit<br />length.<br />Results. A comparison of the complexity and delay in the number of transistors in the decomposition of a multi-bit LUT in the<br />computer mathematics system Mathcad is performed.<br />Conclusions. The conducted researches made it possible to establish the features of constructing multi-bit LUTs and to evaluate<br />various variants of decomposition with further increase in the LUT dimension with the subsequent choice of the optimal ALM variant.
Науковий журнал «Радіоелектроніка, інформатика, управління»
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Tyurin, S. F.; Perm National Research Polytechnic University,
Perm, Russia Grekov, A. V.; Perm Military Institute of National Guard Troops of the Russian Federation, Perm, Russia |
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Сontex. The programmable logic integrated circuits FPGA (field-programmable gate array) used realization of the generator of<br />functions LUT (Look Up Table), which is configured by loading a configuration memory for calculating a logic function in perfect<br />disjunctive normal form (PDNF). The LUT dimension determines the technological limitations of Mead and Conway on the number of<br />series-connected MOS transistors. The standard number of LUT inputs for many years was 3 or 4, and 4-LUT is constructed from two 3-<br />LUTs with an additional 1-LUT. However, in many projects, it is required to calculate functions of a large number of arguments. This<br />requires a multi-input LUT, which is built as a decomposition of 3-LUT, 4-LUT. The speed of computing logic functions determines by the<br />delay in the coupling matrices, so this decomposition leads to a decrease in performance. In recent years, the direction of adaptive logical<br />modules (ALM) has been actively developing, in which the user has access to various versions of logical elements for five, six and even<br />seven, eight variables, which leads to an increase in performance. However, the manufacturer’s documentation does not provide a detailed<br />description of the features of such multi-input LUTs, taking into account the Meade-Conway constraints. In addition, there are no estimates<br />of complexity and speed of multi-input LUTs. The analysis of sources allows suggests a further increase in the LUT bit capacity and the<br />convergence of FPGA and CPLD (complex programmable logic devices) capabilities in terms of bit depth. Therefore, studies of the features<br />of constructing multi-input LUTs are relevant and the authors attempted to analyze the implementation of such prospective multi-bit logic<br />Objective. The purpose of this work is to estimate the complexity and speed of the decomposition of a multi-bit LUT.<br />Method. Obtaining expressions for estimating the complexity and speed of decomposition of a multi-bit LUT on a LUT of a lower bit<br />length.<br />Results. A comparison of the complexity and delay in the number of transistors in the decomposition of a multi-bit LUT in the<br />computer mathematics system Mathcad is performed.<br />Conclusions. The conducted researches made it possible to establish the features of constructing multi-bit LUTs and to evaluate<br />various variants of decomposition with further increase in the LUT dimension with the subsequent choice of the optimal ALM variant. |
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Zaporizhzhya National Technical University 2018-05-29 13:24:17 |
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application/pdf http://ric.zntu.edu.ua/article/view/130868 |
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Radio Electronics, Computer Science, Control; No 1 (2018): Radio Electronics, Computer Science, Control |
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Copyright (c) 2018 S. F. Tyurin, A. V. Grekov |
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