Context. The relevance of the work is to provide minimal additional hardware costs during design automation of easy-tested digital<br />devices, which are represented by models of control finite state machines on hardware description languages.<br />Objective. To develop procedures of models’ constructing of easy-tested control finite state machines on hardware description<br />languages and estimate hardware costs for different methods of hardware redundancy introduction to HDL-models of finite state machines.<br />Method. The introduction to HDL-models of control finite state machines, which are presented in the form of the FSM template,<br />hardware redundancy (additional fragments of the HDL-code), providing the forcing setting of finite state machine into an arbitrary state<br />without the use of synchronizing sequences. For implementation of this approach, the method of FSM’s state table extending is applied,<br />which ensures the mode of bypassing of all nodes of FSM’ state diagram in the diagnostic mode.<br />Results. Simulation of extended VHDL-models of the control FSM using Active-HDL confirmed the operability of this approach.<br />Synthesis of these models using CAD XILINX ISE confirmed the receipt of testable structures and showed the minimum hardware costs for<br />the method associated with the extension of the state table, in comparison with the organization of the shift register in the Scan Path mode.<br />Conclusions. The task of computer-aided design of testable control finite state machine on the basis of application of FSM’ setting<br />methods into given state is solved in the work. The optimal way of the setting organization into an arbitrary state of the control FSM is to<br />expand the state table, which improves the controllability of FSM’ states and leads to the structure’ transformation of their HDL-models<br />into easy-tested ones.<br />The scientific novelty of the work is the transformation of control FSM’ models on hardware description languages, which is realized<br />by introduction of the additional symbol to the state table, providing the settings of the FSM into an arbitrary state without the use of<br />synchronizing sequences.<br />The practical significance of obtained results is to confirm the optimality, in terms of additional hardware costs, of the setting method<br />of the control FSM into an arbitrary state by introducing the additional symbol into the state table.
Науковий журнал «Радіоелектроніка, інформатика, управління»
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Mіrosсhnyk, M. A.; Ukrainian State University of Railway Transport, Kharkiv, Ukraine Pakhomov, Y. V.; Kharkiv National University of Urban Economy, Kharkiv, Ukraine Shkil, A. S.; Kharkiv National University of Radioelectronics, Kharkiv, Ukraine Kulak, E. N.; Kharkiv National University of Radioelectronics, Kharkiv, Ukraine Kucherenko, D. Y.; Kharkiv National University of Radioelectronics, Kharkiv, Ukraine |
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Context. The relevance of the work is to provide minimal additional hardware costs during design automation of easy-tested digital<br />devices, which are represented by models of control finite state machines on hardware description languages.<br />Objective. To develop procedures of models’ constructing of easy-tested control finite state machines on hardware description<br />languages and estimate hardware costs for different methods of hardware redundancy introduction to HDL-models of finite state machines.<br />Method. The introduction to HDL-models of control finite state machines, which are presented in the form of the FSM template,<br />hardware redundancy (additional fragments of the HDL-code), providing the forcing setting of finite state machine into an arbitrary state<br />without the use of synchronizing sequences. For implementation of this approach, the method of FSM’s state table extending is applied,<br />which ensures the mode of bypassing of all nodes of FSM’ state diagram in the diagnostic mode.<br />Results. Simulation of extended VHDL-models of the control FSM using Active-HDL confirmed the operability of this approach.<br />Synthesis of these models using CAD XILINX ISE confirmed the receipt of testable structures and showed the minimum hardware costs for<br />the method associated with the extension of the state table, in comparison with the organization of the shift register in the Scan Path mode.<br />Conclusions. The task of computer-aided design of testable control finite state machine on the basis of application of FSM’ setting<br />methods into given state is solved in the work. The optimal way of the setting organization into an arbitrary state of the control FSM is to<br />expand the state table, which improves the controllability of FSM’ states and leads to the structure’ transformation of their HDL-models<br />into easy-tested ones.<br />The scientific novelty of the work is the transformation of control FSM’ models on hardware description languages, which is realized<br />by introduction of the additional symbol to the state table, providing the settings of the FSM into an arbitrary state without the use of<br />synchronizing sequences.<br />The practical significance of obtained results is to confirm the optimality, in terms of additional hardware costs, of the setting method<br />of the control FSM into an arbitrary state by introducing the additional symbol into the state table. |
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Zaporizhzhya National Technical University 2018-10-04 12:10:39 |
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application/pdf http://ric.zntu.edu.ua/article/view/143183 |
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Radio Electronics, Computer Science, Control; No 2 (2018): Radio Electronics, Computer Science, Control |
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Copyright (c) 2018 M. A. Mіrosсhnyk, Y. V. Pakhomov, A. S. Shkil, E. N. Kulak, D. Y. Kucherenko |
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