Design and simulation of continuously logical analog-to-digital converters with advanced functions for image processors
Репозитарій Вінницького Національного Технічного Університету
Переглянути архів Інформація| Поле | Співвідношення | |
| Title |
Design and simulation of continuously logical analog-to-digital converters with advanced functions for image processors
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| Creator |
Krasilenko, V. G.
Lazarev, A. A. Nikitovich, D. V. Красиленко, В. Г. Лазарєв, О. О. |
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| Description |
The paper considers results of design and modeling of continuously logical analog-todigital converters (CL_ADC) based on current mirrors (CM) with advanced functions of preliminary analogue and subsequent processing for creating sensor multi-channel analog-to-digital converters (SMC ADCs) and image processors (IP). For such with parallel inputs-outputs IP and SMC ADCs it is needed active photosensitive basic cells (BC) with an extended electronic circuit, which are considered in paper. Such BCs and ADCs based on them have a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level for linear and matrix structures. We show design of the BC and CL_ADC of photocurrents and their possible implementations and its simulations. We consider CL_ADC with conversion to binary codes and Gray codes. Each channel of the structure consists of several digital-analog cells (DC) on 15-35 CMOS. The amount of DC does not exceed the number of digits of the formed code, and for an iteration type, only one cell of DC, complemented by the device of selection and holding (SHD), is required. One channel of CL_ADC with iteration is based on one DC-(G) and SHD, and it has only 35 CMOS transistors. In such ADCs easily parallel code can be realized and also serial-parallel output code. The circuits and simulation results of their design with OrCAD are shown. The supply voltage of the DC is 1.8÷3.3V, the range of an input photocurrent is 0.1÷24μA, the transformation time is 20÷30nS at 6-8 bit binary or Gray codes. The general power consumption of the ADC with iteration is only 50÷100μW, if the maximum input current is 4μA. Such simple structure of linear array of ADCs with low power consumption and supply voltage 3.3V, and at the same time with good dynamic characteristics (frequency of digitization even for 1.5μm CMOS-technologies is 40÷50 MHz, and can be increased up to 10 times) and accuracy characteristics are show. The CL_ADCs opens new prospects for realization of photo-electronic structures and IP with matrix operands, which are necessary for neural networks, digital processors fuzzy controllers. |
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| Date |
2018-11-29T08:29:19Z
2018-11-29T08:29:19Z 2018-10 |
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| Type |
Article
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| Identifier |
Krasilenko, V. G. Design and simulation of continuously logical analog-to-digital converters with advanced functions for image processors [Текст] / V. G. Krasilenko, A. A. Lazarev, D. V. Nikitovich // XI Міжнародна науково-практична конференція "Інформаційні технології і автоматизація – 2018", Одеса, 4-5 жовтня 2018 : збірник доповідей. – 2018. – Ч. 1. – C. 12-18.
http://ir.lib.vntu.edu.ua//handle/123456789/22941 621.39 |
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| Language |
en
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| Relation |
XI Міжнародна науково-практична конференція "Інформаційні технології і автоматизація – 2018", Одеса, 4-5 жовтня 2018. Ч. 1 : 12-18.
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application/pdf
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| Publisher |
Одеська національна академія харчових технологій
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