Z Domain Delay Subcircuits and Compact Verilog-A Macromodels for Mixed-mode Sampled Data Circuit Simulation
Електронного архіву Харківського національного університету радіоелектроніки (Open Access Repository of KHNURE)
Переглянути архів Інформація| Поле | Співвідношення | |
| Title |
Z Domain Delay Subcircuits and Compact Verilog-A Macromodels for Mixed-mode Sampled Data Circuit Simulation
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| Creator |
Brinso, M. E.
Nabijou, H. |
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| Subject |
qucs (quite universal circuit simulator)
compact Verilog-A delay macromacromodels functional delay subcircuits mixed-mode sampled data circuit simulation |
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| Description |
Mixed-mode simulation is an important circuit design and system testing tool for established and emerging semiconductor sampled data technologies. This paper describes a number of functional, computationally efficient, Z domain delay models, outlining the role of current and charge equations in the construction of subcircuit and compact Verilog-A delay macromodels. To illustrate the properties of the proposed macromodels a number of Qucs (Quite universal circuit simulator) transient and frequency domain simulation examples are presented. Each of these stresses the use of test and data extraction techniques which are not easily undertaken with the SPICE 2g6 or 3f5 simulators.
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| Date |
2016-08-11T10:59:30Z
2016-08-11T10:59:30Z 2009 |
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| Type |
Article
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| Identifier |
Brinson, M. E. Z Domain Delay Subcircuits and Compact Verilog-A Macromodels for Mixed-mode Sampled Data Circuit Simulation / M. E. Brinson, H. Nabijou // Радиоэлектроника и информатика : науч.-техн. журн. – Х. : Изд-во ХНУРЭ, 2009. – Вып. 2. – С. 14-20.
http://openarchive.nure.ua/handle/document/1810 |
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| Language |
en
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| Publisher |
ХНУРЭ
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