Optimization Factors in Modeling and Testing Hardware and Semiconductor Defects by Dynamic Discrete Event Simulation
Електронного архіву Харківського національного університету радіоелектроніки (Open Access Repository of KHNURE)
Переглянути архів Інформація| Поле | Співвідношення | |
| Title |
Optimization Factors in Modeling and Testing Hardware and Semiconductor Defects by Dynamic Discrete Event Simulation
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| Creator |
Arabian, J. H.
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| Subject |
optimization
semiconductors testing process mapping modeling |
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| Description |
TESTING of Hardware and Product in the Semiconductor Production Process presented a challenge to the collection of data to resolve cost and production issues. As described in reference [1], it has been shown that the Process can be modeled and run with respect to maximizing the output of the model for typical parameters of cost, time, and resources. It remained, however to optimize the human resources with respect to maximizing the output of the model. This paper describes an optimizing technique/tool, which can be used for a manufacturing test process identifying defects to predict/estimate and optimize costs, scheduling and needed resources.
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| Date |
2016-09-01T10:35:22Z
2016-09-01T10:35:22Z 2009 |
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| Type |
Article
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| Identifier |
Arabian, J. H. Optimization Factors in Modeling and Testing Hardware and Semiconductor Defects by Dynamic Discrete Event Simulation / J. H. Arabian // Радиоэлектроника и информатика : науч.-техн. журн. – Х. : Изд-во ХНУРЭ, 2009. – Вып. 2. – С. 21-23.
http://openarchive.nure.ua/handle/document/1905 |
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| Language |
en
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| Publisher |
ХНУРЭ
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