Optimal Memory Tests Coding for Programmable BIST Architecture
Електронного архіву Харківського національного університету радіоелектроніки (Open Access Repository of KHNURE)
Переглянути архів Інформація| Поле | Співвідношення | |
| Title |
Optimal Memory Tests Coding for Programmable BIST Architecture
|
|
| Creator |
Ivaniuk, A. A.
|
|
| Subject |
finite state machines
built-in testing memory testing |
|
| Description |
Programmable memory BIST architecture is becoming a necessity for embedded memory cores. Classical memory BIST architectures use fixed algorithmic tests during the whole live of digital device. To improve the flexibility of memory BIST the programmable solution, based on finite state machine with microcode control, was invented. The requirement to use such flexibility is dictated by reason to use newest test for memory cores. In this paper a new Programmable Memory BIST architecture with small microcode memory is proposed. The analysis of existing March tests allows to code them into the optimal binary format, which cause not only small hardware overhead but also may speed-up the transferring of new test over the serial interfaces like IEEE 1149.1 and P1500.
|
|
| Date |
2016-09-01T10:51:14Z
2016-09-01T10:51:14Z 2008 |
|
| Type |
Article
|
|
| Identifier |
Ivaniuk, A. A. Optimal Memory Tests Coding for Programmable BIST Architecture / A. A. Ivaniuk // Радиоэлектроника и информатика : науч.-техн. журн. – Х. : Изд-во ХНУРЭ, 2008. – Вып. 4. – С. 32-37.
http://openarchive.nure.ua/handle/document/1910 |
|
| Language |
en
|
|
| Publisher |
ХНУРЭ
|
|