General Testing Models of SOC Hardware Software Components
Електронного архіву Харківського національного університету радіоелектроніки (Open Access Repository of KHNURE)
Переглянути архів Інформація| Поле | Співвідношення | |
| Title |
General Testing Models of SOC Hardware Software Components
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| Creator |
Hahanov, V. I.
Litvinova, E. I. Gharibi, W. |
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| Subject |
Infrastructure Intellectual Property
Register Transfer Graph System-on-a-Chip Testing |
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| Description |
Innovative testable design technologies of hardware and software, which oriented on making graph models of SoC components for effective test development and SoC component verification, are considered. A novel approach to evaluation of hardware and software testability, represented in the form of register transfer graph, is proposed. Instances of making of software graph models for their subsequent testing and diagnosis are shown.
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| Date |
2016-09-02T06:48:00Z
2016-09-02T06:48:00Z 2008 |
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| Type |
Article
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| Identifier |
Hahanov, V. General Testing Models of SOC Hardware Software Components / V. Hahanov, E. Litvinova, W. Gharibi // Radioelektronics & informatics : Scientific and Technical Journal. – Kharkiv, 2008. – Вып. 1 (40). – С. 88–96.
http://openarchive.nure.ua/handle/document/1954 |
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| Language |
en
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| Publisher |
KNURE
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