Testing and Verification of HDL-models for SoC components
Електронного архіву Харківського національного університету радіоелектроніки (Open Access Repository of KHNURE)
Переглянути архів Інформація| Поле | Співвідношення | |
| Title |
Testing and Verification of HDL-models for SoC components
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| Creator |
Hahanova, I.
Hahanov, V. Ngene, C. U. Yves, T. |
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| Subject |
HDL-program
Models and methods for verification |
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| Description |
The testing and verification technology for system HDL models, focused to the significant improvement of the quality of design components for digital systems on chips and reduction the development time (time-tomarket) by using the simulation environment, testable analysis of the logical structure HDL-program and the optimal placement of assertion engine is proposed. The novel testing and verification technology for system HDL models allows searching for errors in the HDL-code with a given thoroughness for an acceptable time by means of the introduction assertion redundancy to the critical points of the software model, which are defined by the synthesized logic functions of the testability. The controllability and observability criteria, used in hardware design and test, are applied to estimate the quality of software code in order to improve it and effective diagnose semantic errors. The objective is improvement of the testing and verification technology for digital systems to diagnose and correct of errors for HDL-models by sharing of the assertion engine and testable design technologies. The research tasks: 1. Design verification and testing environment for system HDL-model on the basis of assertions. 2. Development of testability evaluation metrics on the basis of new logic testability function. 3. Application of a technological assertion model to verify an IP-core filter on the basis of discrete cosine transform. 4. Practical results and directions for further research. The research sources: 1. Technologies and tools of test and testbench creation are represented in the papers [1-3]. 2. Models and methods for verification of the system models on the basis of assertions are described in [4-7]. Testable software design uses the IEEE standards [8-10], as well as innovative solutions to verify and testability analysis for the system HDLmodels [11-18].
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| Date |
2016-09-06T07:11:28Z
2016-09-06T07:11:28Z 2009 |
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| Type |
Article
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| Identifier |
Hahanova Irina Testing and Verification of HDL-models for SoC components /Vladimir Hahanov, Irina Hahanova, Ngene Christopher Umerah, Tiecoura Yves //Proceedings of IEEE East-West Design & Test Symposium (EWDTS’09)
http://openarchive.nure.ua/handle/document/2120 |
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| Language |
en
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| Publisher |
EWDTS
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