Verification tests generation features for microprocessor- based structures
Електронного архіву Харківського національного університету радіоелектроніки (Open Access Repository of KHNURE)
Переглянути архів Інформація| Поле | Співвідношення | |
| Title |
Verification tests generation features for microprocessor- based structures
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| Creator |
Krivoulya, G. F.
Shkil, A. S. Syrevitch, Ye. Antipenko, O. |
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| Subject |
design verification and validation
test generation multibit implication range method HDL |
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| Description |
A model of a microprocessor - based device as a bichromatic multidigraph with vertexes of two types is offered. Test generation features for functional testing using the updated algorithm of path activation in a structural model are described. The range method of data representation of different format data is introduced. Algorithms for execution of direct implication and backtracing of different types of operations and their program realization are represented. All set of methods of the determined test generation for digital devices can be divided into two large groups: structural and functional. Originally structural methods were oriented to a gate level of model performance of digital devices. However growth of complexity and rise of a component integration have led to a fact that models of increased integration elements began to be applied as the primitive elements (PE) of devices [1,2]. To the advantages of such approach it is possible to refer simple construction of a model of the device and formalizing of test generation procedures, and to the lacks - large dimension of a device model; and difficulties on creation and maintaining of the library of PE models, which can contain hundreds components. With the purpose of overcoming these lacks the functional approach to construction of the tests was developed and has received a wide circulation [3, 4]. It can be used for digital devices of any complexity, including microsystems with program and microprogram control, as it allows receiving high level models of such devices. However functional methods are badly formalized because different types of function boxes, such as control block, operational block, address block etc. are present in microsystems. It is not obviously possible to formalize the method, which would have a possibility to handle so heterogeneous types of devices on the basis of the uniform approach. In the given work the method of tests generation which is further development of the functional approach is offered. On a design stage of the digital device its decomposition on so-called homogeneously tested segments is carried out. The authors consider a method of tests generation for one of types of segments, namely, for the operational device (OD).
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| Date |
2016-09-06T09:16:49Z
2016-09-06T09:16:49Z 2004 |
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| Type |
Article
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| Identifier |
Syrevitch Yevgeniya Verification tests generation features for microprocessor- based structures/Gennadiy Krivulya, Alexandr Shkil, Yevgeniya Syrevitch, Olga Antipenko //Proceedings of East-West Design & Test Workshop (EWDTW’04)
http://openarchive.nure.ua/handle/document/2136 |
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| Language |
en
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| Publisher |
EWDTW
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